Etch and Dry Strip

Our Broad Technology Platform Solves Critical Thin Film Etching Challenges

As electronic consumer devices continue to become smaller and lighter with increased performance, advanced packaging pushes the limits of innovation in the semiconductor industry. Advanced packaging has evolved to keep pace with industry needs to reduce package size, decrease power consumption and increase chip connectivity while improving reliability, performance and multi-function integration. As advanced packaging processes and 3D integration drive back-end adaptations of front-end processes, MKS Instruments’ extensive experience as a front-end manufacturing supplier helps us understand, anticipate and support the changing needs of the back-end packaging environment. MKS, a long standing solutions supplier for front-end semiconductor fabrication has partnered with our customers solving their most challenging advanced packaging problems, leveraging our technical innovation, experience and passion.

Chip packaging technology that meets industry expectations of size, power, yield, and cost continues to evolve with new advanced packaging chip methods including 3D and 2.5D glass and silicon interposers. These new and unique processes to interconnect and integrate chips into final assemblies present new challenges in deposition, etch, singulation and clean for both front-end foundries and back-end packaging suppliers.

New Challenges in Etch Processes

Through-Silicon Via (TSV) is the feature that enables 2.5D and 3D advanced packaging. Via pathways are short vertical columns through the silicon wafer or die that form electrical connection pathways. Vias enables smaller package sizes by removing the need for external wire bonds, support more dense interconnects, improve electrical performance by shortening the electrical distance traveled, and enable stacking of multiple chips used in products like High Bandwidth Memory (HBM).

High aspect ratio via formation, TSV reveal, and surface passivation are key etch process steps in advanced packaging that require high ratio selectivity capabilities. Achieving consistent and repeatable etch characteristics for each of these process steps while increasing throughput is critical as it directly impacts yield, overall reliability, and product quality of the final packaged chip.

Challenges specific to Etch include:

  • Minimizing reflected power for consistent via etch depth
  • High selectivity ratio for deep, high aspect ratio vias
  • Surface passivation for higher yield
  • Precise profile control for subsequent uniform layer deposition and fill

Etch Process Solutions

Reliable RF Power

The Bosch process etches Through-Silicon Vias using a rapidly alternating etch and deposition cycle. MKS’ RF Power Generators and improve the reliability of the power generator optimizing the Bosch process. As plasma is used during the process it leads to a change in system impedance. The rapid Bosch cycle causes continuous impedance changes resulting in reflected power. Our RF Generators offer Dynamic Frequency Tuning as fast as 50 µsec to keep up with these rapid impedance changes. This ensures power is delivered to the load reliably and consistently leading to a more efficient process and repeatable etch rates. RF Generators and Match Networks also provide a way to quickly adapt to the changing impedance levels created when etching through different layers of material resulting in a good uniform etch process.

Once the TSV is created, it needs to be revealed in order to expose the TSV nodes for the redistribution layer (RDL). The reveal is done by a combination of back side grind and plasma etch. Back side grind is used to remove the silicon down to within 5-10 micrometers of the TSV node. For plasma etch to complete the TSV reveal, an RF Generator is used as the plasma etch power source and provides exceptional performance by delivering consistent plasma power with high selectivity ratio to material, excellent reliability and power levels proven to be higher than competitive offerings.

Plasma Sources

After exposing the TSV nodes and prior to the RDL step, a passivation layer serves as a protective film against metal contaminants that can impact device yield. MKS’ Plasma Source solution, based on either a microwave or low-field toroidal RF source, provides high density active radicals to create a protective oxide layer on the wafer surface. This layer not only protects the surface from further contaminants and moisture, it also protects specific areas from the next process step and makes the surface hydrophilic for easier cleaning. MKS’ highly efficient Microwave and low-field toroidal Remote Plasma Sources enable fast throughput during the passivation process.

Pressure Measurement and Flow Control

MKS’ best-in-class Baratron® Capacitance Manometers measure pressure/vacuum in the chamber and provide the front-end level of control necessary to achieve a good wafer. This is also useful in advanced packaging applications where pressure/ vacuum control are just as critical to achieve reliable vias in etch and passivation processes. Mass Flow Controllers, in situ Mass Flow Verifiers, and Flow Ratio Controllers which accurately and repeatably divide gas flows into precise flow streams to multiple points in the process for improved process uniformity and control.

Semiconductor Devices and Process Technology Handbook

For additional information on the semiconductor etch process as well as other semiconductor applications please download our free Semiconductor Devices and Process Technology eBook.

Etch Products